Circuit designers have at their disposal, a variety of different methods of implementing their circuit designs. One method involves incorporating their designs in dedicated custom integrated circuits (ICs). The initial cost is relatively high and the turn-around time for producing a first set of these semiconductor chips is relatively long. Another method involves the implementation of application-specific integrated circuits (ASICs). Time to market for ASICs are faster, and it is easier to implement design changes. A third alternative, which enjoys growing popularity, is utilizing programmable logic devices (PLDs).
A PLD is a semiconductor chip that contains an array of gates having programmable interconnections. The gates are programmed according to the specification provided by the circuit designer, thereby resulting in the desired logic functions. The programming usually involves using a piece of hardware, known as a programmer. A programmer is typically coupled by a serial port to a microcomputer, on which some form of programmer software is run. The simplest kind of software enables a designer to select which fuses to burn. The designer decides the desired logic function, at the gate level, then lists the corresponding fuses. Other more sophisticated programmers allow designers to specify Boolean expressions or truth tables. The software handles the minimization, simulation, and programming steps automatically. This yields custom combination and even sequential logic on a PLD chip.
There are basically two variants of PLDs: programmable array logic (PALs.TM.) and programmable logic arrays (PLAs). They are available in both bipolar and CMOS construction. PALs.TM. use fusible-link (one-time-programmable), whereas PLAs use floating-gate MOS (ultraviolet or electrically erasable). The differences between them are in respect to programming flexibility. PALs.TM. are typically faster, cheaper, and easier to program, but PLAs are more flexible. Programming of both types of devices is limited by their built-in structure.
In both cases, the desired logic functions are implemented by using standard product terms (p-terms). This involves first performing an AND function on the input variables and then forming the sum of the products, usually by performing an 0R function. Typically, a standard number of p-terms are input to a programmable output structure, known as a macrocell.
Historically, when PLDs were first introduced, they tended to be simple and were rather limited in the functions that they could perform. Because of their limited resources, the early PLD designs typically could only be initialized to a given, predetermined state. For example, the PLD could be initialized to output all 0's or they could be initialized to output all 1's. Likewise, the PLDs could typically be reset to only the all 0's or all 1's state. Often, the PLD could only be reset synchronous to the system clock.
Now, with advances in semiconductor technology, PLDs have become bigger, and more complex. The functions of entire blocks of circuitry can be performed by a single PLD. Although modern PLDs are more powerful than their predecessors, some of the deficiencies associated with earlier PLD designs have, nonetheless, carried over into present day PLD designs. One of the deficiencies found in many modem PLD designs is that they cannot be initialized or reset to a user defined state. Typically, modern PLD designs only allow for initialization and resets to either the all 0's or all 1's state.
The disadvantage with this arrangement is that circuit designers wishing to use PLDs are constrained to initializing and resetting the PLD in a pre-determined state. It is not possible to have the PLD output a particular digital state other than all 0's or all 1's upon power-up. Under some circumstances, it would be beneficial, if not necessary, to have the PLD power-up in a particular user defined digital sequence other than all 0's or all 1's. Due to the constraint imposed by typical prior art PLDs, circuit designers must forgo using a PLD in their designs or must design around this limitation.
Once the PLD is up and running, a product term is typically implemented to provide an asynchronous reset. When the PLD is reset, it is typically reset to either the all 1's or all 0's state. Although a circuit designer has the flexibility to determine under what circumstances the PLD is to be reset by specifying the product term dedicated to the reset function, circuit designers often are not provided with the capability of specifying a particular digital state for output upon detecting a reset. This imposes a burden on circuit designers wishing to reset to a particular digital state. Again, circuit designers are forced to design around this contingency.
Thus, what is needed is an apparatus and method for providing a circuit designer with the flexibility of specifying a particular digital state to which a PLD is initialized. There is also a need in the prior art for extending that flexibility so that the PLD can be reset to any particular digital state. It would be highly preferable if both the initialization and resetting functions could be performed asynchronously.